Integrity of PCB design signal

Integrity of PCB design signal

Signal integrity refers to the quality of a signal on a signal line, that is, the ability of a signal to respond in the circuit with the correct timing and voltage. If the signal in the circuit can reach the receiver at the required timing, duration, and voltage amplitude, then the circuit can be determined to have better signal integrity. Conversely, when the signal does not respond properly, a signal integrity problem occurs.

With the use of high-speed devices and the increasing design of high-speed digital systems, system data rates, clock rates, and circuit intensities are constantly increasing. In this design, the system has fast slope transients and high operating frequencies, and cables, interconnects, printed boards (PCBs), and silicon will exhibit behavior that is distinct from low-speed designs, ie, signal integrity issues. Signal integrity issues can cause or directly introduce such things as signal distortion, timing errors, incorrect data, addresses, control lines and system errors, and even crash the system, which has become a very interesting issue in high-speed product design.

Problems with PCB signal integrity include: Signal integrity issues of the PCB mainly include signal reflection, crosstalk, signal delay, and timing errors.

1. Reflection: When the signal is transmitted on the transmission line, when the characteristic impedance of the transmission line on the high-speed PCB does not match the source impedance or load impedance of the signal, the signal will be reflected, causing the signal waveform to overshoot, undershoot and thereby cause Ringing phenomenon. Overshoot is the first peak (or valley) of a signal transition, which is an additional voltage effect above the power supply level or below the ground level; Undershoot is the signal jump. Change to the next valley (or peak). Excessive overshoot voltage often causes long-term impact damage to the device, undershooting reduces noise margin, and ringing increases the time required for signal stabilization, which affects system timing.

2. Crosstalk: In PCB, crosstalk refers to the undesired noise interference caused by electromagnetic energy to adjacent transmission lines through mutual capacitance and mutual inductance when the signal propagates on the transmission line. It is the electromagnetic field caused by different structures. Produced by interactions in the same area. The mutual capacitance induces a coupling current called capacitive crosstalk; and the mutual inductance induces a coupling voltage called inductive crosstalk. On the PCB, crosstalk is related to the length of the trace, the spacing of the signal lines, and the condition of the reference ground plane.

3. Signal delay and timing error: The signal is transmitted at a limited speed on the PCB conductor, and the signal is sent from the driver end to the receiver end with a transmission delay. Excessive signal delay or signal delay mismatch can cause timing errors and logic device turbulence.

High-speed digital system design and analysis based on signal integrity can not only effectively improve product performance, but also shorten product development cycle and reduce development costs. In the case of the development of digital systems in the direction of high speed and high density, it is very urgent and necessary to master this design tool. The digital system design method for computer design and analysis using signal integrity will be widely and comprehensively applied in the continuous improvement and improvement of the signal integrity analysis model and computational analysis algorithm.

PCB signal integrity steps:

1. Pre-design preparation Before design begins, you must first think about and determine the design strategy to guide such things as component selection, process selection, and board production cost control. In the case of SI, research is conducted in advance to form planning or design guidelines to ensure that the design results do not exhibit significant SI problems, crosstalk or timing issues.

2. Stacking of circuit boards Some project groups have a great autonomy in determining the number of PCB layers, while other project groups do not have this autonomy. Therefore, it is important to know where you are. Other important questions include: What are the expected manufacturing tolerances? What is the expected insulation constant on the board? What is the allowable error of line width and spacing? What is the allowable error in the thickness and spacing of the ground plane and signal layer? All of this information can be used during the pre-wiring phase.

Based on the above data, you can choose to cascade. Note that almost every PCB that plugs into other boards or backplanes has thickness requirements, and most board manufacturers have fixed thickness requirements for different types of layers that they can make, which will greatly limit the number of final stacks. . You may want to work closely with the manufacturer to define the number of cascading. Impedance control tools should be used to generate target impedance ranges for different layers, making sure to take into account the manufacturing tolerances and adjacent wiring provided by the manufacturer. In the ideal case of complete signal, all high speed nodes should be routed within the impedance control inner layer (eg stripline). To optimize the SI and keep the board decoupled, the ground plane/power plane should be placed in pairs as much as possible. If you only have a pair of ground plane/power planes, you will only be there. If there is no power layer at all, you may encounter SI problems by definition. You may also encounter situations where it is difficult to simulate or simulate the performance of a board before the return path of the signal is defined.

3. Crosstalk and Impedance Control Coupling from adjacent signal lines will cause crosstalk and change the impedance of the signal line. Coupling analysis of adjacent parallel signal lines may determine the "safe" or expected spacing (or parallel routing length) between signal lines or between various types of signal lines. For example, to limit the crosstalk of the clock to the data signal node to within 100mV, but to keep the signal traces parallel, you can find the minimum allowable spacing between the signals on any given wiring layer by calculation or simulation. Also, if the design contains nodes with important impedances (either clocks or dedicated high-speed memory architectures), you must place the traces on one layer (or layers) to get the desired impedance.

4. Important high-speed node delays and skews are key factors that must be considered for clock routing. Because of the tight timing requirements, such nodes typically must use termination devices to achieve the best SI quality. These nodes are pre-determined and the time required to adjust component placement and routing is planned to adjust the pointer for signal integrity design.

5. Technology selection Different drive technologies are suitable for different tasks. Is the signal point-to-point or point-to-multiple? Is the signal output from the board or on the same board? What is the allowed time lag and noise margin?

As a general guideline for signal integrity design, the slower the conversion speed, the better the signal integrity. There is no reason for the 50MHZ clock to have a 500PS rise time. A 2-3NS slew rate control device is fast enough to guarantee the quality of the SI and to help solve problems such as output synchronous switching (SSO) and electromagnetic compatibility (EMC). The advantages of drive technology can be found in new FPGA programmable technologies or user-defined ASICs. With these custom (or semi-custom) devices, you have a lot of room to choose the drive amplitude and speed. At the beginning of the design, the FPGA (or ASIC) design time is required to meet the appropriate output choices and, if possible, pin selection. At this stage of design, a suitable simulation model is obtained from the IC supplier. In order to effectively cover the SI simulation, you will need an SI simulation program and the corresponding simulation model (probably the IBIS model). Finally, during the pre-wiring and routing phases you should create a series of design guidelines that include: target layer impedance, routing spacing, device technology that is preferred, critical node topology, and termination planning.

6. Pre-wiring stage The basic process of pre-wiring SI planning is to first define the input parameter range (drive amplitude, impedance, tracking speed) and possible topological range (min/max length, short line length, etc.), then run each possible simulation. Combine, analyze timing and SI simulation results, and finally find acceptable ranges of values. Next, the working range is interpreted as the wiring constraints of the PCB layout. This type of "cleaning" preparation can be performed using different software tools, and the routing program can automatically handle such wiring constraints. For most users, timing information is actually more important than SI results, and the results of the interconnect simulation can change the routing to adjust the timing of the signal path. In other applications, this process can be used to determine the placement of pins or devices that are not compatible with system timing pointers. At this point, it is possible to completely determine the nodes that need to be manually routed or the nodes that do not need to be terminated. For programmable devices and ASICs, the choice of output driver can also be adjusted at this point to improve the SI design or avoid discrete termination devices.

7. SI simulation after wiring In general, the SI design guidelines are difficult to ensure that SI or timing problems do not occur after the actual wiring is completed. Even if the design is guided by the guide, unless you can continue to automatically check the design, there is no guarantee that the design will fully comply with the guidelines, so problems will inevitably occur. Post-wiring SI simulation checks will allow for planned breaks (or changes) in design rules, but this is only necessary for cost considerations or strict wiring requirements.

8. After the manufacturing phase, the above measures can be taken to ensure the SI design quality of the board. After the board assembly is completed, it is still necessary to place the board on the test platform. The oscilloscope or TDR (time domain reflectometer) measurement will be true. The board is compared to the expected results of the simulation. These measurements help you improve your model and manufacturing parameters so you can make better (less constraints) decisions in your next pre-design survey.

9. Model Selection There are many articles on model selection. Engineers who perform static timing verification may have noticed that although all data can be obtained from the device data table, it is still difficult to build a model. The SI simulation model is just the opposite. The model is easy to build, but the model data is difficult to obtain. Essentially, the only reliable source of SI model data is the IC supplier, who must maintain a tacit understanding with the design engineer. The IBIS model standard provides a consistent data carrier, but the establishment of the IBIS model and the guarantee of its quality are costly. IC suppliers still need market demand for this investment, and circuit board manufacturers may be the only demanders. market.

PCB design method to ensure signal integrity: By summarizing the factors affecting signal integrity, signal integrity is well ensured in the PCB design process, which can be considered from the following aspects.

(1) Circuit design considerations. Including controlling the number of synchronous switching outputs, controlling the maximum edge rate (dI/dt and dV/dt) of each unit to obtain the lowest and acceptable edge rate; selecting differential signals for high output function blocks (such as clock drivers); Passive components (such as resistors, capacitors, etc.) are connected to the upper end to achieve impedance matching between the transmission line and the load.

(2) Minimize the trace length of the parallel wiring.

(3) The components should be placed away from the I/O interconnection interface and other areas susceptible to interference and coupling, and the spacing between components should be minimized.

(4) Shorten the distance between the signal traces to the reference plane.

(5) Reduce the trace impedance and signal drive level.

(6) Terminal matching. Terminal matching circuits or matching components can be added.

(7) Avoid parallel wiring of the traces, provide sufficient trace spacing between traces, and reduce inductive coupling.

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