Via Design in High Speed PCB
Via Design in High Speed PCB
Through the above analysis of via parasitics, we can see that in high-speed PCB design, seemingly simple
Holes often also bring great negative effects to the design of circuits. In order to reduce the adverse effects of parasitic effects of vias,
You can do as much as possible in the design:
1.From the perspective of cost and signal quality, choose a reasonable size of via hole size, such as for the inner layer of 6-10 layers.
For the design of the memory module PCB, it is better to use 10 / 20Mil (drilling / pad) vias.For some high-density small-sized
For boards, you can also try to use 8 / 18Mil vias. At present, it is difficult to use smaller vias. Yes
For power or ground vias, consider using a larger size to reduce impedance.
2.The two formulas discussed above can be concluded that the use of thinner PCBs is conducive to reducing the two types of vias.
Parameters.
3.The signal traces on the PCB board should not change layers as much as possible, that is, try not to use unnecessary vias.
4, the power and ground pins should be punched nearby, the lead between the via and the pin should be as short as possible, because they will
This leads to an increase in inductance. At the same time, the power and ground leads must be as thick as possible to reduce the impedance.
5.Place some grounded vias near the vias of the signal layer to provide the nearest loop for the signal.
A lot of extra ground vias are placed on the PCB. Of course, the design also needs to be flexible. The vias discussed earlier
The model is the case where there are pads on each layer, and sometimes we can reduce or even remove pads on some layers. Especially
In the case of very high via density, it may lead to the formation of a break slot in the copper layer to cut off the circuit.
In addition to moving the position of the via, we can also consider reducing the pad size of the via in the copper layer.
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